1. Field of the Invention
The present invention relates to an amplifier circuit used in audio systems.
2. Discussion of the Related Art
FIG. 1 shows a conventional audio bridge tiled load (BTL) amplifier circuit. The circuit comprises two inverter-assembled operational amplifiers 11 and 12. The inverting input (−) of amplifier 11 is connected to an input terminal E of the system by a resistor 13 and a coupling capacitor 14 connected in series. Output O1 of amplifier 11 is connected to its inverting input (−) by a resistor 15. The inverting input (−) of amplifier 12 is connected to output O1 of amplifier 11 by a resistor 16 and to its output O2 by a resistor 17. The respective outputs O1 and O2 of amplifiers 11 and 12 are connected to the terminals of a load 18, typically a loudspeaker capable of emitting sounds according to the current flowing therethrough. The non-inverting inputs (+) of amplifiers 11 and 12 are connected to a common node BP. Node BP is connected to the midpoint of a resistive divider comprising two resistors 19 and 20 connected in series between a supply terminal VCC and ground GND. A controllable switch 21, generally an MOS transistor, is interposed between supply terminal VCC and resistor 19. A standby control signal SB controls switch 21 and the power supply of amplifiers 11 and 12. In a setting to standby, signal SB causes the setting to a high-impedance state of the outputs of amplifiers 11 and 12 and the turning-off of switch 21, which results in a significant reduction in power consumption. A capacitor 22 is connected between node BP and ground, in parallel with resistor 20. Capacitor 22 has the function of filtering the noise generated by resistors 19 and 20 and of absorbing possible variations of the voltage at supply terminal VCC.
The gain of amplifier 11 is given by the ratio of resistances 15 and 13. The gain of amplifier 12 is generally chosen to be equal to −1 by setting an identical value for both resistors 16 and 17.
The expression of voltage V18 across load 18 is then provided by the following equation:V18=VO1−VO2=−2(R15/R13)*(VM−VBP)
where R13 and R15 are the respective values of resistors 13 and 15, and VO1, VO2, VBP, and VM respectively are the voltages at outputs O1 and O2 of amplifiers 11 and 12, at node BP, and at a node M between capacitor 14 and resistor 13.
The divider formed of resistors 19 and 20 sets the voltage at node BP, and thus the charge level of capacitor 22, to a reference voltage setting a bias voltage of the audio amplifier. For example, the reference voltage may be chosen to be equal to half of supply voltage VCC, and resistances 19, 20 are then set to the same value. In normal operation, in the absence of a signal at input terminal E, the charges of capacitors 14 and 22 are equal, voltages VM and VBP are equal to the reference voltage, the voltage across load 18 then being zero. When a voltage is applied to input terminal E, voltage VM is equal to the reference voltage, to which adds the variable component of the input voltage, with coupling capacitor 14 suppressing the D.C. component of the input voltage.
Voltage V18 across load 18 is equal to the variable component of the input voltage multiplied by amplification gain −2R15/R13. By choosing an appropriate ratio of resistances 15 and 13, the peak-to-peak load voltage can be significantly amplified.
FIGS. 2A to 2E are partial simplified timing diagrams illustrating the variation of voltages along time at certain points of the amplifier circuit of FIG. 1 on a powering-on of the device, that is, when the supply voltage rises from 0 volt to nominal level VCC. FIG. 2A illustrates voltage VBP at node BP, that is, the variation of the charge of decoupling capacitor 22. FIG. 2B illustrates voltage VM at node M, that is, the variation of the charge of coupling capacitor 14. FIG. 2C illustrates voltage VO1 at output O1 of amplifier 11. FIG. 2D illustrates voltage VO2 at output O2 of amplifier 12. FIG. 2E illustrates voltage V18 across load 18. A starting time of the circuit of FIG. 1, either from a completely off state, or from a standby state, is considered as the time origin (t=0).
Upon circuit power-on, the supply voltage almost immediately switches from 0 volt to VCC. Voltage VBP at node BP stabilizes with the shape of a capacitor charge to the reference voltage, for example VCC/2. Voltage VM at node M also stabilizes at reference voltage VCC/2. Voltages VM and VBP reach their balanced level VCC/2 substantially at the same time, generally from 50 to 150 ms after power-on. However, as illustrated by a comparison of FIGS. 2A and 2B, voltage VM exhibits a delay upon power-on with respect to voltage VBP, then reaches the balanced level at faster speed. Indeed, capacitor 14 charges faster than capacitor 22, but its charge starts with a delay, since it is performed through capacitor 22, by copying of the voltage level, through resistor 13, from node BP to node M. This charge delay translates as a difference between voltages VM and VBP, voltage VM remaining smaller than voltage VBP until the balanced state is reached. Operational amplifiers 11 and 12 supplied by supply voltage VCC being almost “immediately” operative, the difference between the voltages at nodes M and BP is reflected on their respective outputs O1 and O2. Thus, as illustrated in FIG. 2C, voltage VO1 at output O1 of amplifier 11 is very high upon power-on while voltage VO2 at output O2 of amplifier 12 still is zero, as illustrated in FIG. 2D. This difference translates, across load 18, as a very high voltage V18 upon power-on, often sufficient to cause a characteristic unpleasant audible noise.
To overcome this problem, various solutions have been provided. In particular, circuits comprising a relay in series with the load and switched after a delay sufficiently long for all transient variations of the amplifier circuit to have disappeared have been provided. However, such circuits are impossible to use in small-size devices such as mobile phones or walkmans due to the bulk of the relay, which is difficult to integrate.
It is also known to modify the circuit to sufficiently slow down the charges of capacitors 14 and 22 so that, at any time, the charges are substantially equal, thus reducing the difference between the voltages of nodes M and BP. The overvoltage across the load is then reduced and the corresponding residual noise is reduced to a level which is less unpleasant for the user, or even inaudible. However, this improvement is obtained at the cost of a significant lengthening of the latency time, that is the starting time during which the device is unusable, which may reach values on the order of one to two seconds. Such values are incompatible with most applications, especially telephone applications.
Further, conventional solutions impose a compromise between reduced latency times and a high capacity of the circuit for rejecting possible power supply disturbances (PSSR, power supply rejection ratio). Indeed, to minimize latency times, it would be suitable to minimize the capacitance of input coupling capacitor 14 and the resistance “seen” from the supply terminal. This would alter the capacity of the circuit for rejecting possible power supply disturbances.